Apparatus for automatically measuring time intervals using multiple interpolations of any fractional time interval

ABSTRACT

An apparatus for measuring a time interval between first and second pulses includes a counter which counts pulses from a first oscillator which is turned on by the first pulse. When the second pulse occurs a second oscillator operates a second counter to determine the fractional time interval, if any, resulting whenever the second pulse occurs between pulses of the first oscillator. A coincidence detector arrangement determines when the first and second oscillators are in phase. At such time the second oscillator is stopped for a fixed period of time, and then it is connected to a third counter for another vernierizing operation. Successive vernierizing operations may be performed by connecting the second oscillator to successive counters in turn under control of the coincidence detector arrangement.

United States Patent Inventor Appl. No.

Filed Patented Assignee APPARATUS FOR AUTOMATICALLY MEASURING TIMEINTERVALS USING MULTIPLE INTERPOLATIONS OF ANY FRACTIONAL TIME INTERVALPrimary Examiner-Alfred E. Smith Attorneys-Edwin M. Thomas, Ralph L.Thomas and Thomas & Thomas ABSTRACT: An apparatus for measuring a timeinterval between first and second pulses includes a counter which countspulses from a first oscillator which is turned on by the first pulse.When the second pulse occurs a second oscillator operates a secondcounter to determine the fractional time interval, if any, resultingwhenever the second pulse occurs between pulses of the first oscillator.A coincidence detector arrangement determines when the first and secondoscillators l2 Chums 5 Drawing are in phase. At such time the secondoscillator is stopped for U.S.Cl.... 324/187 a fixed period of time, andthen it is connected to a third lnt.Cl G04f 9/00, counter for anothervernierizing operation. Successive ver- G04f 11/06 nierizing operationsmay be performed by connecting the Field of Search 324/68, 83 secondoscillator to successive counters in turn under control D; 328/129 ofthe coincidence detector arrangement.

20 r F so so 100 l m 056 I e v e O .couNTER l #1 .0 I 0 50 10 ,90

l 0 l 0 F l FF ss A Ill T f START STOP L 112 PHASE COINCIDENCE I 32DETECTOR STOP,

T IF e| m |0| lI Wu OSC COUNTER 2 I G G O 2 l l START I I a-/ l ,5] 4|,9: ,2! o l l o L I FF ss A 1 l I L- l APPARATUS FOR AUTOMATICALLYMEASURING TIME INTERVALS USING MULTIPLE INTERPOLATIONS OF ANY FRACTIONALTIME INTERVAL BACKGROUND OF THE INVENTION This invention relates toapparatus for measuring time intervals and more particularly to suchapparatus for performing multiple interpolations.

In some of the earlier arrangements for automatically measuring a timeinterval, the interval being defined by the lapse of time between firstand second pulses, a first oscillator is turned on by the first pulse,and the pulses are counted by a first counter. Ifthe time interval isnot equal exactly to a multiple number of cycles of the firstoscillator, a fractional portion of the cycle of the first oscillatormust be measured and this measure is made by a second or vemieroscillator. The vemier oscillator is turned on by the second pulse, andits pulses are counted in a second counter until the two oscillatorsreach coincidence. Alternatively, the first oscillator may be freerunning and vemier interpolation may be utilized for estimatingfractional counts at the beginning and end of the timed period. Thisrequires a vemier oscillator for each of the two interpolations unlessthe timed period is long enough to permit timing out of the beginninginterpolation before the end interpolation is undertaken. Moreover, thesmallest increment of the measurement remaining is the simple differencebetween the main and vemier oscillator periods of oscillation.

SUMMARY OF THE INVENTION It is a feature of this invention to provide animproved arrangement for automatically measuring a time interval moreaccurately.

It is a further feature of this invention to measure automatically thetime interval between a pair of signals with greater accuracy by using amain oscillator and a vemier oscillator to perform multiple successivelyfiner interpolations.

It is a feature of this invention to provide an improved arrangement formeasuring the time interval between a pair of signals by using a mainoscillator with a first counter to count the number of whole cycles ofthe main oscillator and a single vemier oscillator which perfonns two ormore vemierizing operations with two or more additional counters todetermine successively lower order parts of a fractional period of themain oscillator.

It is a further feature of this invention to provide an apparatus formeasuring the time interval between a pair of signals wherein the timeinterval T includes a unit time interval T which is determined bycounting pulses from a main oscillator and a plurality of fractionaltime intervals T T T etc., which are obtained by counting pulses from asingle vemier oscillator in successive vemierizing operations.

In a preferred arrangement according to this arrangement a plurality ofcounters are employed, and a control stage is provided for each counter.A first or main oscillator is connected through the associated controlstage to the first counter, and it determines the number of whole countsin the unit time interval T,. A second or vemier oscillator is connectedto the remaining control stages. A phase coincidence detector receivespulses from both of the oscillators, and it is connected to a switchmechanism such as a ring circuit. Various stages of the ring circuit areconnected to given control stages whereby each control stage may beoperated in tum for determining successively lower order fractions T Tetc., in the time interval T,. The output of the phase coincidencedetector is supplied also tqzthe vemier oscillator, and the vemieroscillator is stopped between vemierizing operations.

A time, interval to be measured is defined by first and second pulses.The first pulse starts the main oscillator and activates'the firstcontrol stage whereby pulses from the main oscillator are counted inreal time in the first counter. When the second pulse arrives, therebyterminating the time interval under measurement, the first control stageis deactivated, the vemier oscillator is started, and the control stageassociated with the second counter is activated whereby pulses from thevemier oscillator are counted by the second counter which determines thefractional time interval T When the phase coincidence detector signalrises, vemier stops the vemier oscillator, vemier the second controlstage, and after a fixed time delay it advances the switch mechanismwhich in turn activates the third control stage and starts the vemieroscillator whereby the third counter counts pulses from the vernieroscillator to determine the fractional time interval T2. Successivevemierizing operations may be performed. When the last vemierizingoperation is terminated, the main oscillator is turned off, and themeasurement of the time interval is finished. The time during which thesecond and subsequent counters are operated takes place in what may becalled expanded time where this term indicates the lapse of a relativelylong period of time during which vemierizing operations take place todetermine relatively small fractional time intervals.

The foregoing and other objects, features and advantages of theinvention will be apparent from the following more particulardescription of a preferred embodiment of the invention, as illustratedin the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1 and 2 illustrate in block forma system according to this invention for automatically measuring a timeinterval.

FIG. 3 illustrates the manner in which FIGS. 1 and 2 should be arrangedwith respect to each other.

FIG. 4 illustrates in detail the phase coincidence detector shown inblock form in FIG. 1.

FIGS. 5A through 50 show waveforms which are helpful in describing theoperation of the system in FIGS. 1 and 2.

DESCRIPTION OF THE PREFERRED EMBODIMENT Reference is made to FIGS. 1 and2 which illustrate a counter arrangement according to this invention.FIGS. 1 and 2 should be arranged with respect to each other asillustrated in FIG. 3. A plurality of counters 10 through 13 areprovided. A plurality of control stages 20 through 23 control thepassage of pulses to the respective counters 10 through 13. A mainoscillator 30 and a vemier oscillator 31 provide pulses for operatingthe various counters. A phase coincidence detector 32 responds tosignals from both oscillators, and when the oscillator signals are inphase, a distinctive output signal is provided to the control stages 20through 23, the oscillator 31, and through a delay circuit 33 to a ringcircuit 34. The ring circuit is provided with three stages in thearrangement shown, and stages 2 and N provide output signals on therespective lines 41 and 42 to an OR circuit 43. The lines 41 and 42 areconnected to respective control stages 22 and 23. An AND circuit 44 inFIG. 2 is provided for terminating a counting operation, and itsoperation is described more fully hereinafter.

The control stages 20 through 23 include associated flip flops 50through 53, and their one output sides are connected to correspondinggates 60 through 63. The control stages 20 through 23 also includeassociated single shots 70 through 73. and their zero output sides areconnected to respective gates through 83. The control stages 20 through22 include associated And circuits through 92 which are connected torespective Or circuits through 102. The OR circuits 100 through 102 areconnected to respective counters 10 through 12. The output of the gate83 in FIG. 2 is connected directly to the counter 13.

A flip-flop in FIG. 1 controls the oscillator 30. The oscillator 30 isoperated when the flip-flop 110 is set in the one binary state by apositive signal on the input line 111. The oscillator 30 is turned offwhen the flip-flop 110 is reset to the zero state by a positive signalon the line 45 from the And circuit 44 at the end of a countingoperation.

When a given time interval is to be measured, its commencement isrepresented by the leading edge of a positive signal applied to the line1 I 1, and the termination of the time interval is represented by theleading edge of a positive signal on the line 112. The given timeinterval is measured by summing the content of the counters 10 through13. The counter 10 is operated in real time during the occurrence of thetime interval to be measured, and the counters 11 thru 13 are operatedin expanded time after termination of the time interval to be measured.

Reference is made next to FIG. 4 which illustrates in detail the phasecoincidence detector 32 which is shown in block form in FIG. 1. Signalsfrom the oscillator 30 are supplied on the line 113 and to an ANDcircuit 115, and signals from the oscillator 31 are supplied on the line114 to the AND circuit 1 15. When both input signals to the AND circuit115 are positive, the AND circuit provides a positive output signal, andif either of the input signals is negative, the AND circuit 115 providesa negative output signal. Output signals from the AND circuit 1 15 aresupplied to the zero input side of a single shot 120. Positive signalsfrom the AND circuit 115 force the single shot 120 into the binary zerostate which is its unstable state. As long as positive signals arereceived at the zero input of the single shot 120, it remains in thezero state, and a positive signal from the binary zero output side issupplied to the binary one input side of a flip-flop 121. The singleshot 120 serves as a digital integrator. This sets the flip-flop 121 tothe binary one state, and a negative output signal appears on the line122 from the zero output side of this flip-flop. The output signal fromthe AND circuit 115 in FIG. 4 is connected also through a diode 130 to adifferential amplifier 132. A condenser 133 and a resistor 134 serve asan analog integrator. A variable bias source in the form of a battery135 is connected as a second input to the differential amplifier 132.Positive signals from the AND circuit 1 15 are passed by the diode 130,and they charge up the condenser 133. The condenser 133 and the resistor134 serve to average or integrate the positive signals from the ANDcircuit 115, and the averaged value of these signals is supplied on theline 131 to the differential amplifier 132. Whenever the signal on theinput line 131 is more positive than the signal on the input line 136,the differential amplifier 132 provides a negative output signal.Whenever the positive signal level on the line 131 becomes equal or lessthan the bias signal level on the line 136, the differential amplifier132 provides a positive output signal. This positive output signal issupplied to the zero input side of the flip-flop 121 which resets thisflip-flop, and the flip-flop 121 then provides a positive output signalon the line 122. The condenser 133 and the resistor 134 serve as ananalog integrator which activates the phase coincidence detector, andthe single shot 120 serves as a digital integrator which deactivates thephase coincidence detector.

The basic function performed by the counting arrangement in F108. 1 and2 is that of measuring a time interval which commences with the leadingedge of a positive start pulse on the line 111 and terminates with theleading edge of a positive stop pulse on the line 112 in FIG. 1. Adescription of the operation of the system in FIGS. 1 and 2 is givennext.

A positive start pulse on the line 112 sets the flip-flops 50 and 110 inFIG. 1 and resets the single shot 70. When the flipflop 110 is set tothe one state, a positive output signal from the one output side causesthe oscillator 32 to supply pulses on the line 113 to the phasecoincidence detector 32 and the gate 60. The phase coincidence detectordoes not receive pulses from the oscillator 31 at this time, and theoutput signal therefrom on the line 122 is a positive level. Thispositive level conditions the associated input to the AND circuit 90 inF IG. 1 the oscillator pulses supplied to the gate 60 are passed to thegate 80 because the flip-flop 50 is in the one state, thereby supplyinga positive "signal to the gate 60. The single shot 70, however, is resetto the zero state, its unstable state, and the gate 80 is deconditionedby a negative signal level from the one output side of the single shot70. The single shot 70 remains in its unstable zero state for a timeperiod approximately equal to one cycle of the oscillator 30.Consequently, the first oscillator pulse from the oscillator 30 is notpassed by the gate 80. However, the single shot 70 automatically resetsto the one state by the time the second pulse from the oscillator 30 isgenerated, and the single shot 70 then conditions the gate 80.Therefore, the second and subsequent pulses from the oscillator 30 passthrough the gates 60 and to the Or circuit which in turn passes suchpulses to the counter 10. The second and subsequent pulses from theoscillator 30 advance the counter 10, and the counter is advanced bysuccessive pulses from the oscillator 30 until a positive stop signal isreceived on the line 112 in FIG. 1. At such time the flip-flop 50 isreset which establishes a negative signal on its one output side thatdeconditions the gate 60 and prevents the passage of further pulses fromthe oscillator 30 to the counter 10. The positive stop signal on theline 112 is supplied also to the one input side of the flip-flop 51, thezero input side of the single shot 71, and the OR circuit 43 in FIG. 1.The positive signal is passed by the OR circuit 43 to the oscillator 31,and the oscillator thereby is operated to supply pulses on the line 114to the gate 61. The positive pulse on the line 112 sets the flip-flop51, and its one output side supplies a positive signal which conditionsthe gate 61 to pass positive pulses from the oscillator 31. The positivepulse on the line 112 resets the single shot 71, and its one output sidesupplies a negative signal which deconditions the gate 81. The singleshot 71 remains in the zero state for a period of time equalapproximately to one cycle of the oscillator 31. Therefore, the gate 81does not pass the first positive pulse from the oscillator 31. Thesingle shot 71 reverts to its set state automatically by the end of thefirst cycle of the oscillator 31., and its one output side supplies apositive signal which conditions the gate 81 to pass the second andsubsequent positive pulses from the oscillator 31. These pulses passthrough the OR circuit 101 to the counter 11, and the counter isadvanced by successive pulses from the oscillator 31. Pulses from theoscillator 31 continue to advance the counter 11 until the oscillator 31is stopped by a positive signal from the phase coincidence detector 32.The phase coincidence detector 32 supplies a negative output signal whenthe oscillator 30 and 31 are out of phase, and it supplies a positivesignal on the line 122 when the phase difference of the two oscillatorsbecomes zero. At such time the positive signal on the line 122 stops theoscillator 31 and resets the flip-flop 51 thereby to decondition thegate 61. The positive signal on the line 122 is supplied also throughthe delay circuit 33 in H0. 2 to the ring circuit 34, and the ringcircuit is advanced from the first to the second stage. The ring circuitthen provides a positive signal on the line 41 to the OR circuit 43which in turn passes this signal to the oscillator 31. This causes theoscillator 31 to operate again. The positive pulse on the line 41 setsthe flip-flop 52 in FIG. 2 and resets the single shot 72. Thisconditions the gate 62 so that positive oscillator pulses on the line114 are supplied through the gate 62 to the gate 82. The single shot 72deconditions the gate 82, and this inhibits the passage of the firstpositive pulse from the oscillator 31. The single shot automaticallysets by the end of the first cycle of the oscillator 31, and the secondand subsequent pulses pass through the gate 62, the gate 82, and the ORcircuit 102 to the counter 12. The counter 12 counts successive pulsesfrom the oscillator 31 until the phase coincidence detector 32 againdetermines that the oscillators 30 and 31 are in phase, and it thensupplies a positive signal on the line 122. At such time the positivesignal on the line 122 resets the flip-flop 52 and deconditions the gate62, thereby inhibiting the passage of any further pulses from theoscillator 31 to the counter 12. The positive signal on the line 122stops the oscillator 31. The positive signal on the line 122 is suppliedthrough the delay circuit 33 in FlG. 2 to the ring circuit 34. The ringcircuit .34 advances from stage 2 to stage N. The ring circuit 34 thensupplies a positive signal on the line 42 which is passed by the ORcircuit 43 in FIG. 1 to start the oscillator 31 again. The positivesignal on the line 42 is supplied to the one input side of flip-flop 53and the zero input of the single shot 73. The first pulse from theoscillator 31 is passed by the gate 63. However, this pulse is blockedby the gate 83 because the single shot 73 is reset to the zero state atthis time, and it supplies a negative signal from the one output sidewhich deconditions the gate 83. By the end of the first cycle of theoscillator 31 the single shot 73 is automatically set, and it supplies apositive signal from the one output side which conditions the gate 83 topass the second and subsequent positive pulses from the oscillator 31.These pulses are supplied to the counter 13, and the counter is advancedby successive pulses until the phase detector 32 in FIG. 1 determinesthat the oscillators 30 and 31 are in phase. At this time phasecoincidence detector 32 supplies a positive signal on the line 122 whichresets the flip-flop 53, and it supplies a negative signal from the oneoutput side which deconditions the gate 63. The positive signal on theline 122 is supplied also through the delay circuit 33 to the ringcircuit 34, and the ring circuit is advanced from stage N to stage 1. Apositive signal is supplied at the output of stage 1, but it is notused. With stage 1 set and the remaining stages reset, the ring circuitis in the reset condition. The positive signal on the line 122 issupplied also to the AND circuit 44 in FIG. 2, and for a short time thisAND circuit simultaneously receives a positive output signal from theone output side of the flip-flop 53. The AND circuit 44 supplies apositive pulse on the line 45 which resets the flip-flop 110 in FIG. 1.It is pointed out that the positive output signal from AND circuit 44 isof brief duration, and its width is determined by the time required toset the flip-flop 53. The output from the AND circuit 44 is used to endthe counting operation, and it may be used for other purposes such astransferring the content of the various counters through 13 to otherequipment.

The AND circuits 90 through 92 in respective control stages 20 through22 serve an add-one function. This function is provided to removeambiguities which would otherwise exist when coincidence signals rise ateven multiples of the oscillator 01 signals. The AND circuit 90 respondsto the inverse of a positive signal from the phase coincidence detector32 on the line 122 and a positive signal from the zero output side ofthe single shot 71 of the control stage 21, and the AND circuit 90provides a positive output signal which is passed by the OR circuit 100to advance the counter 10 by the value of one count. It should be notedthat this occurs only if a signal sufficient to fire single shot 120occurs during the window provided by single shot 71. The AND circuit 91in the control stage 21 responds to the inverse of single on the line122 and a positive signal from the zero output side of the single shot72 in the control stage 22, and the AND circuit 91 supplies a positiveoutput signal through the OR circuit 101 to advance the counter 11 bythe value of one count. The AND circuit 92 in FIG. 2 responds to theinverse of a positive signal on the line 122 and a positive from thezero output side of the single shot 73 in the control circuit 23, andthe AND circuit 92 passes a positive signal through the OR circuit 102to advance the counter 12 by the value of one count. The counter 10 isadvanced by the value of one count with the positive pulse from the ANDcircuit 90 after the control stage 21 is activated. The counter 11 isadvanced by the value of one count with the positive pulse from the ANDcircuit 91 after the control stage 22 is activated. The counter 12 isadvanced by the value of one count with the positive pulse from the ANDcircuit 92 after the control stage 23 is activated.

In order to illustrate more precisely the operation of the countersystem according to this invention, let it be assumed that a timeinterval of 204.05 units is to be measured. The oscillator 30 and theoscillator 31 have different frequencies. The greater the difference inthe frequencies, the more rapidly the two oscillators approach the pointof being in phase. Stated alternatively, as the frequency differencebetween the two oscillators becomes less and less, the longer it takesfor them to reach the in phase condition. There are a wide range ofchoices in the selection of the frequencies of the oscillators. It ispointed out that as the time interval to be measured becomes shorter induration, the frequencies of the oscillators preferably are increased inorder to obtain greater accuracy in the measurement. Thus for someapplications the frequencies of the oscillators may be in the kilocycleranges; whereas, for other applications the frequencies of theoscillators may be in the megacycle range or even higher, depending onthe particular application. If, for example, the time interval of 204.05units represents nanoseconds, then the oscillator 30 may have afrequency of 10 megahertz, and the oscillator 31 may have a frequency ofl0.l megahertz.

Reference is made to FIG. 5 which shows the waveforms of the variouscircuits in FIGS. 1 and 2 when a time interval of 204.05 units ismeasured. This interval of time is depicted in FIG. 5A and it occursbetween a first pulse on the line 111 and a second pulse on the line 112in FIG. 1. The commencement of the time interval to be measured isrepresented by a positive pulse on the line 111 in FIG. 1, and thispulse sets the flip-flop to the one state. The positive signalestablished on its one output side to the oscillator 30 is shown in FIG.5A. The leading edge in FIG. 5A defines the commencement of the timeinterval to be measured. The positive level from the one output side ofthe flip-flop 110 in FIG. 1 continues until the termination of thecounting operation of the system in FIGS. 1 and 2, and the mainoscillator 30 runs during this period. The termination of the countingoperation takes place at the time indicated by the trailing edge 151 ofthe positive pulse in FIG. 5A, and this transition takes place when theflip-flop 110 in FIG. 1 is reset by a positive signal from the ANDcircuit 44 in FIG. 2.

When the flip-flop 1 10 is in the one state, the oscillator 30 is turnedon, and the pulses from the oscillator 30 are illustrated in FIG. 5C aspulses through 171. These pulses are supplied to the gate 60 in FIG. 1and the phase coincidence detector 32. Since the oscillator 31 is notoperated at this time, the phase coincidence detector 32 supplies apositive signal level on its output line 122 as illustrated in FIG. 5H.The positive signal on the line 122 in FIG. 1 and FIG. 2 resets theflip-flops 51 through 53in respective control stages 21 through 23, andthis inhibits any counting operations in the vemier counters 10 through13.

The positive start pulse on the line 111 in FIG. 1 sets the flip-flop 50and resets the single shot 70. The signal from the one output side ofthe flip-flop 50 conditions the gate 60 to pass pulses from theoscillator 30, and this gate passes the pulses 160 and 161 in FIG. 5B.The positive start pulse on the line 1 1 1 resets the single shot 70 toits zero or unstable state. Consequently, a negative signal from the oneoutput side of the single shot 70 deconditions the gate 80 for one cycleof the oscillator 30. This is shown in FIG. 5.]. As a result the pulse160 in FIG. 5C is not passed by the gate 80 in FIG. 1. At or subsequentto the trailing edge of the pulse 160 in FIG. 5C the single shot 70 inFIG. 1 returns to its stable binary one state, ad shown in FIG. SJ, andthe gate 80 in FIG. 1 passes subsequent pulses from the oscillator 30.In this instance it passes the pulse 161 in FIG. 5C through the ORcircuit 100 in FIG. 1 to the counter 10. This positive pulse advancesthe counter from a zero setting to the value of one.

A positive stop pulse occurs on the line 112 in FIG. 1. and it occursbetween the oscillator pulses 161, and 162 in FIG. 5C. The positive stoppulse on the line 112 resets the flip-flop 50, and this establishes anegative signal level from the one output which deconditions the gate 60and inhibits the passage of further pulses from the oscillator 30through the gate 60. The positive pulse on the line 112 is suppliedthrough the OR circuit 43 in FIG. 1, and it starts the oscillator 31which then supplies positive pulses on the output line 114. The leadingedge of the stop pulse on the line 112 is substantially identical to theleading edge of the first pulse from the oscillator 31, and this pulseis the pulse in FIG. 5D. The positive stop pulse on the line 112 setsthe flip-flop 51 in FIG. 1 and resets the single shot 71. The controlstage 21 thereby is conditioned. and the counter 11 is incrementedsubsequently. However, the add one function performed by the AND circuit90 for the control stage 20 takes place at this time. The positiveoutput signal from the phase coincidence detector 122 continues, asshown in FIG. 5H, until the pulse in FIG. 5E occurs. The inverse of thelevel on line 122 is supplied to AND circuit 90, and the AND circuit 90receives a positive signal from the zero output side of the single shot71 which is reset at this time. The one output side of the single shot71 is a negative level as shown by the negative pulse 200 in FIG. L. Itis during the negative pulse 200 that the zero output side of the singleshot 71 provides a positive level to the AND circuit 90. Consequently,the AND circuit 90 supplies a positive pulse to the OR circuit 100, andthis positive pulse is shown in FIG. 5M. The OR circuit 100 in FIG. 1passes this positive pulse, shown as pulse 201 in FIG. 5K, to thecounter 10, and it is incremented from the value of one to the value oftwo. It is pointed out that the counter is operated in real time.

An increment of time must be vemierized in order to measure preciselythe time interval between the start pulse supplied to the line 111 inFIG. 1 and the stop pulse supplied to the line 112. The incremental timeperiod is shown between FIGS. 5D and 5E, and it lies between thetrailing edge of the pulse 161 in FIG. SC and the leading edge of thepulse 180 in FIG. 5D. To vernierize or interpolate this time incrementis the function of the counters 1 I through 13.

The pulse 190 in FIG. 5E originates in the AND circuit 115 in FIG. 4.The pulse 190 represents the period of time that the oscillator pulse162 in FIG. 5C is positive and the oscillator pulse 180 in FIG. 5Dsimultaneously is positive. The pulse 190 represents the overlappedportions of the oscillator pulses. The positive pulse 190 is supplied tothe zero input side of the single shot 120 in FIG. 4. The output signalfrom the zero output side of the single shot 120 is represented by thewaveforms in FIG. 50. The positive output signal from the single shot120 is represented by the pulse 210 in FIG. 5G. This positive signal issupplied to the one input side of the flip-flop 121, and this flip-flopis set to the one state. As a result the signal from the zero outputside of the flip-flop 120 on the line 122 Changes from a positive to anegative level, and this is indicated by the negative pulse 215 in FIG.5H. As soon as the single shot 71 in FIG. 1 returns to its stable binaryone state, as represented by the termination of the negative pulse 200in FIG. 51., the counter 11 in FIG. 1 commences to receive pulses fromthe oscillator 31. The pulse 180 in FIG. 5D from the oscillator 31 isinhibited by the single shot 71 as previously explained. However, thepulses 181 through 183 in FIG. 5C from the oscillator 31 are passedthrough the gate 61, the gate 81, and the OR circuit 101 to the counter11. The pulses supplied to the counter 11 are shown in FIG. 5N, and theyare labeled 181 through 183. These pulses successively advance thecounter 1 1 from the count of zero to the count of three.

As the pulses 181 through 183 increment the counter 11, they alsooperate the AND circuit 115 FIG. 4 in conjunction with pulses from theoscillator 30. The output from the AND circuit 115 is a sequence ofpulses 190 through 193, and each is successively narrower than thepreceding one. The pulse 193 is so narrow that it is not able to resetthe single shot 120 in FIG. 4 and hold it in the unstable binary zerostate. Consequently, the positive pulse 210 in FIG. G terminates as thesingle shot I reverts to the stable binary one state. This causes anegative signal level to be supplied from the zero output side of thesingle shot 120 to the one input side of the flipflop 121. This negativesignal is represented by the pulse 211 in FIG. 50. The pulses 190through 193 in FIG. 5E are supplied through the diode 130 in FIG. 4 tothe analog integrator circuit including the condenser 133 and theresister 134. These pulses charge the condenser 133. The signal from theanalog integrator is shown in FIG. SF. The pulse 190 is the first tocharge the condenser 133, and it provides the greatest charge. Eachsucceeding pulse provides progressively smaller charges. The condenserdischarges through the resister 134 at a rate determined by the RC timeconstant. The successive pulses 191 through 193 add successively smallerincremental charges to the condenser 133.

Since the condenser 133 is constantly discharged and since eachsucceeding pulse supplies a progressively smaller charge, it followsthat the average charge on the condenser is reduced with time. Thewaveform in FIG. 5F is idealized in the interest of simplicity toindicate the integrated or average charge with respect to time. When thecondenser 133 is discharged sufficiently by the resister 134 such thatthe positive signal level on the line 131 is less than the positivesignal level on the line 136, then the output signal from thedifferential amplifier 132 changes from a negative signal level to apositive signal level. The positive signal level from the differentialamplifier 132 resets the flip-flop 121, and a positive signal levelappears on the line 122. This is represented by the positive pulse 216in FIG. 51-1.

The positive signal on the line 122 in FIG. 1 resets the flipflop 51,and the positive pulse from the one output side of the flip-flop 51,shown in FIG. 5B, is terminated. The positive signal level on the line122 conditions one input to the AND circuit 91 and stops the oscillator31. The positive signal level on the line 122 is supplied through thedelay circuit 33 to the ring circuit 34. The delay circuit 33 permitssufficient time delay for the oscillator 31 to discharge and recoverbefore it is started again. This delay is illustrated in FIG. 51.

The ring circuit 34 is advanced from stage 1 to stage 2, and it suppliesa positive pulse on the line 41 which sets the flipflop 52, resets thesingle shot 72, and passes through the OR circuit 43 and restarts theoscillator 31. When the flip-flop 52 in FIG. 2 is set, it supplies apositive signal from its one output side. This positive signal is shownin FIG. 51, and it conditions the gate 62 to pass positive pulses fromthe oscillator 31. The single shot 72, being temporarily reset to theunstable binary zero state, supplies a negative output signal from thebinary one output side which deconditions the gate 82. The negativesignal from the binary one output side is shown as a negative pulse 230in FIG. 50. The positive signal from the binary zero output side of thesingle shot 72, coincident in time with pulse 230, is supplied to theAND circuit 91 in FIG. 1. The other input to the AND circuit 91 is thepositive signal 216 in FIG. 5I-I on the line 122 from the phasecoincidence detector 32. Consequently, the AND circuit 91 in FIG. 1supplies a positive signal through the OR circuit 101 to the counter 11,thereby advancing this counter from the value of 3 to the value of 4.The positive signal from the AND circuit 91 is shown as a pulse 231 inFIG. 5P. It is seen that the AND circuit 91 performs its add onefunction after the delay occasioned by the delay circuit 33 in FIG. 2.

The first pulse 184 in FIG. 5D from the oscillator 31 is not passed bythe gate 82 in FIG. 2, and it is lost. The single shot 72 in FIG. 2automatically sets to the stable binary one state prior to the arrivalof the second oscillator pulse 185 in FIG. 5D. The second and subsequentpulses 185 through 188 in FIG. 5D from the oscillator 31 in FIG. I arepassed by the gate 62, the gate 82, and the OR circuit 102 to thecounter 12, and these pulses are shown in FIG. 50. The counter 12 isadvanced successively from zero to a count of four. When the phasecoincidence detector 32 detects phase coincidence between the pulses ofthe oscillators 30 and 31, the positive signal it supplies on the line122 resets the flip-flop 52 in FIG. 2 and conditions the AND circuit 92.The positive signal on the line 122 advances the ring circuit in themanner previously explained, and it supplies a positive signal on theline 42 which sets the flip-flop 53 and resets the single shot 73 inFIG. 2. The

positive signal from the zero output side of the single shot 73conditions the other input to the AND circuit 92, and it supplies apositive pulse to the counter 12 which advances the counter from thecount of 4 to the count of 5. The timing relationships of the signalsfor causing the AND circuit 92 to perform its add one function are notshown in FIG. 5 in the interest if simplicity. They are similar to therelationships described above with respect to the control stage 21. Fora more precise measurement of any time increment such as the one underconsideration, additional stages may be provided. For the illustrativeexample above, however, the counter 13 is not required. Its operation isreadily understood from the foregoing description. It is pointed outthat the counter 13 is not advanced in the illustrative example.Therefore, when the counting operation is terminated by a positivesignal from the AND circuit 44 in FIG. 2, the counter 10 holds thequantity 2, and this represents 200 time units; the counter 11 holds thevalue 4, and this represents 04 time units; the counter 12 holds thevalue 5, and this represents 0.05 time units. The operation of thevernier counters 10 through 12 takes place in expanded time. Thus it isseen how the counting systems in FIGS. 1 and 2 operates to measureprecisely a time interval which lies between a start pulse on the lineIII in FIG. 1 and a stop pulse on the line 1 12.

It is pointed out by way of summary that the counting arrangement inFIGS. 1 and 2 is an improved system which uses a single vemieroscillator. The use in the phase coincidence detector 32 of a digitalintegrator, such as the single shot 120 in FIG. 4, and an analogintegrator, such as the condenser 33 and the resistor 134 in FIG. 4,permit the employment of low speed circuits in the construction of thecounter system in FIGS. 1 and 2, thereby reducing costs. An additionaladvantage is the ability to extend the technique to yield additionalorders of precision in time measurements. The time interval between thestart and stop pulses is defined as real time, and pulses from theoscillator 30 are counted during this period by the counter 10. Onreceipt of a stop signal the counting in real time stops, and the timeinterval between the rise of the stop signal and the end of theconversion, as indicated by a positive signal from the AND circuit 44 inFIG. 2, is referred to as expanded time. For example, 100 pulses appliedto the counter 11 have the same weight as one pulse applied to thecounter 10. In like fashion I pulses applied to the counter 12 have thesame weight as one pulse applied to the counter 11'. The time expansiontechnique employed in the counting arrangement according to thisinvention is an improved modification of the vemier oscillator techniqueemployed in earlier systems. In such earlier systems the vemieroscillator operates a counter the value of which is proportional to thephase difference between a main oscillator and the vemier oscillator.The main oscillator is turned on when a start signal is applied, andpulses from this oscillator are used to operate a counter in real time.The vemier, oscillator is turned on when a stop signal is applied, andpulses from the vemier oscillator are gated to a different counter untilthe two oscillator signals become coincident, thereby providingadditional interpolation of the last cycle of the main oscillator. Thefrequency of the vemier oscillator establishes the resolution of thecounting system. If the main oscillator uses megahertz and the vemieroscillator uses 10.1 megahertz, for example, this yields a closing rateof l nanosecond per cycle. Thus, each pulse of the vemier oscillatorrepresents 1/100 of the time of the main oscillator or I nanosecond. Atthe time of coincidence between the main oscillator and the vemieroscillator, an accuracy of one nanosecond is established. That is, thecoincidence signal may have occurred with i 500 picoseconds of actualcoincidence. The vemier technique might be further expanded by using thecoincidence signal to turn on a second vemier to repeat the foregoingprocess until coincidence occurs between the second vemier oscillatorand the main oscillator, and the pulses counted during this operationconstitute a further definition of the last cycle of the first vemieroscillator or 1/100 of l nanosecond. The process may be repeated withadditional third, fourth, etc., vemier oscillators.

In the improved arrangement according to this arrangement, however,multiple vernier oscillators are not employed. Instead, the same vemieroscillator is used for each vernierizing operation. The vemieroscillator is stopped upon each detected coincidence with the mainoscillator, and after a fixed delay it is restarted. The pulses from thevemier oscillator are supplied to a different counter for eachvernierizing operation. Thus it is seen that the arrangement accordingto this invention provides simplification of the circuitry employed andsimplification of calibration. Theoretically, successive reentries inthe time expansion technique according to this invention may be repeatedas often as required to obtain the desired accuracy'. The expansionfactor increases exponentially for each reentry. For example, a thirdreentry using a 10 megahertz main oscillator and a 10.1 megahertz vemieroscillator yield an expansion factor of or 0.1 picosecond resolution. Asa matter of practice, however, limits on the number of reentries, andhence the precision of measurements, are determined by the limitationsof the circuits employed.

In order to produce a coincidence signal with sufficient precision toallow reentry, the phase coincidence detector 32 must be accurate, andthe increased accuracy is obtained by the use of the digital integratorand the analog integrator in the circuit arrangement of FIG. 4. Theanalog integrator provides an output signal which is proportional to thedifference between the two oscillator signals. Only one cycle of thiscircuit is required to perform a level of time expansion. The output ofthe analog integrator is used to terminate a given entry by stopping thevemier oscillator and turning it on after a fixed time delay. Thedigital integrator in FIG. 4 is used to signify the rise of thedifference frequency signal.

It provides an initial signal for dropping the output 122 of thedetector 32 as soon as a difference signal is present and formaintaining that output in that condition as long as the differencesignal pulse train (FIG. 5, E) continues. This insures a stable outputat 122 until capacitor 133 has been charged and the analog branch of thedetector has achieved stable operation. It will be apparent that any ofa wide variety of missing pulse detectors could be employed for thispurpose. Single shot is shown as a simple illustration. Details of aspecific circuit of this kind are shown, for example, in the IBMTechnical Disclosure Bulletin, Vol. 11, No. II (Apr. 1969), pages1512-1513.

While the invention has been particularly shown and described withreference to a preferred embodiment thereof, it will be understood bythose skilled in the art that various changes in form and details may bemade therein without departing from the spirit and scope of theinvention.

What is claimed is:

1. An apparatus for measuring automatically a time interval betweenfirst and second pulses,

the apparatus having a main oscillator and a first counter which countssignals from the main oscillator during said time interval between thefirst and second pulses, said first pulse serving to turn on the mainoscillator,

vemier oscillator means and a plurality of additional counters forperforming successive interpolation operations on any time intervaloccurring between the last oscillator signal and the second pulse,

a phase coincidence detector connected to the main oscillator and thevemier oscillator for indicating phase coincidence of the signals fromboth of said oscillators, and

switch means connected between the phase coincidence detector, thevemier oscillator means and the additional counters, said switch meansoperating under control of the phase coincidence detector to connect thevemier oscillator to each of the additional counters in turn forperforming successive interpolation operations in each of the additionalcounters with each successive interpolation operations in each of theadditional counters with each successive interpolation operationproviding a finer measurement of the fractional time interval remainingafter the preceding interpolation operation.

2. The apparatus of claim I wherein the switch means includes a ringcircuit which is advanced by the phase coincidence detector upon phasecoincidence of the main oscillator and the vemier oscillator means, andthe vemier oscillator means is connected to each of the additionalcounters in turn for performing successive interpolation operations.

3. The apparatus of claim 1 wherein the phase coincidence detectorincludes:

a digital integrator which responds to overlapped signals from the mainoscillator and the vemier oscillator to deactivate the phase coincidencedetector, and

an analog'integrator which responds to overlapped signals from the mainoscillatorand the vemier oscillator to detect phase coincidence of thetwo oscillators and activate the phase coincidence detector.

4. An apparatus for measuring automatically a time interval betweenfirst and second pulses,

the apparatus having a main oscillator and a first counter which countssignals from the main oscillator during the time interval between thefirst and second pulses,

a vemier oscillator and a plurality of additional counters,

a phase coincidence detector connected to the main oscillator and thevemier oscillator for indicating phase coincidence of the signals fromboth of said oscillators,

a plurality of control stages, one for each additional counter, meansconnected each control stage to an associated additional counter,

a switch device connected between the phase coincidence detector, thevemier oscillator and the plurality of control stages, said switchdevice operating under control of the pulse coincidence detector toconnect the vernier oscillator through the control stages to theassociated additional counters in turn for performing successiveinterpolation operations in each of the additional counters.

5. The apparatus of claim 4 wherein the switch device is a ring circuitwhich is advanced by the phase coincidence detector upon phasecoincidence of the main oscillator and the vemier oscillator, and thevemier oscillator is connected through the control stages to theadditional counters in turn for performing successive interpolationoperations.

6. The apparatus of claim 4 wherein the phase coincidence detectorincludes:

a digital integrator which responds to overlapped signals from the mainoscillator and the vemier oscillator to deactivate the phase coincidencedetector, and

an analog integrator which responds to overlapped signals from the mainoscillator and the vemier oscillator to detect phase coincidence of thetwo oscillators and activate the phase coincidence detector.

7. The apparatus of claim 6 wherein the digital integrator is missingpulse detector comprising a single shot, and the analog integrator is acondenser and a resister connected in parallel.

8. An apparatus for measuring automatically a time interval betweenfirst and second pulses,

the apparatus including a main oscillator, a first control stageconnected to the main oscillator, and a first counter connected to saidfirst control stage, said control stage and said oscillator beingoperated by the first pulse to supply pulses from the main oscillator tosaid first counter whereby said first counter is operated in real time,

a vemier oscillator, a plurality of additional control stages, meansconnecting the vemier oscillator to each of said additional stages,

a plurality of additional counters, means connecting said additionalcontrol stages to said additional counters,

means responsive to the second pulse for starting the vemier oscillator,activating the first of said plurality of additional control stages, anddeactivating said first control stage,

a phase coincidence detector connected to the main oscillator and thevemier oscillator for indicating phase coincidence of the twooscillators, a ring circuit connected to the plurality of additionalcontrol stages, said phase coincidence detector having an output lineconnected to said vernier oscillator, said additional control stages,and said ring circuit for stoppingthe vemier oscillator, deactivatingsaid additional control stages, and advancing said ring circuit wheneversaid phase coincidence detector detects coincidence of the mainoscillator and the vemier oscillator, means connecting the ring circuitto the vemier oscillator for starting the vernier oscillator each timethe ring circuit is advanced, delay means connected in series with thering circuit for delaying the start of said vernier oscillator, saidring circuit operating a given one of the additional control stages eachtime it is advanced by the phase coincidence detector, whereby theadditional control stages are operated in turn, means responsive to theoperation of the last of said plurality of additional control stages forstopping the main oscillator.

9. The apparatus of claim 8 wherein the phase coincidence detectorincludes:

a digital integrator which responds to overlapped signals from the mainoscillator and the vemier oscillator to deactivate the phase coincidencedetector, and

an analog integrator which responds to overlapped signals from the mainoscillator and the vemier oscillator to detect phase coincidence of saidmain and vernier oscillators and activate the phase coincidencedetector.

10. The apparatus of claim 9 wherein the digital integrator is a singleshot, and the analog integrator is a condenser and a resistor connectedin parallel.

11. The apparatus of claim 10 wherein the digital integrator includes aflip-flop having one and zero inputs, said single shot having an outputline connected to the one input of the flipflop,

a differential amplifier having two inputs, means connecting the analogintegrator to one of said inputs, a fixed source of bias potentialconnected to the other input of said differential amplifier, saiddifferential amplifier having an output connected to the zero input ofsaid flip-flop, said flip-flop having a zero output line connected tosaid vernier oscillator and said control stages for stopping said vemieroscillator and deactivating said control stages.

12. The apparatus of claim 11 wherein the phase coincidence detectorincludes an AND circuit connected to receive signals from the mainoscillator and the vemier oscillator, and said AND circuit having anoutput line connected to said single shot and said analog integrator.

1. An apparatus for measuring automatically a time interval betweenfirst and second pulses, the apparatus having a main oscillator and afirst counter which counts signals from the main oscillator during saidtime interval between the first and second pulses, said first pulseserving to turn on the main oscillator, vernier oscillator means and aplurality of additional counters for performing successive interpolationoperations on any time interval occurring between The last oscillatorsignal and the second pulse, a phase coincidence detector connected tothe main oscillator and the vernier oscillator for indicating phasecoincidence of the signals from both of said oscillators, and switchmeans connected between the phase coincidence detector, the vernieroscillator means and the additional counters, said switch meansoperating under control of the phase coincidence detector to connect thevernier oscillator to each of the additional counters in turn forperforming successive interpolation operations in each of the additionalcounters with each successive interpolation operations in each of theadditional counters with each successive interpolation operationproviding a finer measurement of the fractional time interval remainingafter the preceding interpolation operation.
 2. The apparatus of claim 1wherein the switch means includes a ring circuit which is advanced bythe phase coincidence detector upon phase coincidence of the mainoscillator and the vernier oscillator means, and the vernier oscillatormeans is connected to each of the additional counters in turn forperforming successive interpolation operations.
 3. The apparatus ofclaim 1 wherein the phase coincidence detector includes: a digitalintegrator which responds to overlapped signals from the main oscillatorand the vernier oscillator to deactivate the phase coincidence detector,and an analog integrator which responds to overlapped signals from themain oscillator and the vernier oscillator to detect phase coincidenceof the two oscillators and activate the phase coincidence detector. 4.An apparatus for measuring automatically a time interval between firstand second pulses, the apparatus having a main oscillator and a firstcounter which counts signals from the main oscillator during the timeinterval between the first and second pulses, a vernier oscillator and aplurality of additional counters, a phase coincidence detector connectedto the main oscillator and the vernier oscillator for indicating phasecoincidence of the signals from both of said oscillators, a plurality ofcontrol stages, one for each additional counter, means connected eachcontrol stage to an associated additional counter, a switch deviceconnected between the phase coincidence detector, the vernier oscillatorand the plurality of control stages, said switch device operating undercontrol of the pulse coincidence detector to connect the vernieroscillator through the control stages to the associated additionalcounters in turn for performing successive interpolation operations ineach of the additional counters.
 5. The apparatus of claim 4 wherein theswitch device is a ring circuit which is advanced by the phasecoincidence detector upon phase coincidence of the main oscillator andthe vernier oscillator, and the vernier oscillator is connected throughthe control stages to the additional counters in turn for performingsuccessive interpolation operations.
 6. The apparatus of claim 4 whereinthe phase coincidence detector includes: a digital integrator whichresponds to overlapped signals from the main oscillator and the vernieroscillator to deactivate the phase coincidence detector, and an analogintegrator which responds to overlapped signals from the main oscillatorand the vernier oscillator to detect phase coincidence of the twooscillators and activate the phase coincidence detector.
 7. Theapparatus of claim 6 wherein the digital integrator is missing pulsedetector comprising a single shot, and the analog integrator is acondenser and a resister connected in parallel.
 8. An apparatus formeasuring automatically a time interval between first and second pulses,the apparatus including a main oscillator, a first control stageconnected to the main oscillator, and a first counter connected to saidfirst control stage, said control stage and said oscillator beingoperated by the first pulse to supply pulSes from the main oscillator tosaid first counter whereby said first counter is operated in real time,a vernier oscillator, a plurality of additional control stages, meansconnecting the vernier oscillator to each of said additional stages, aplurality of additional counters, means connecting said additionalcontrol stages to said additional counters, means responsive to thesecond pulse for starting the vernier oscillator, activating the firstof said plurality of additional control stages, and deactivating saidfirst control stage, a phase coincidence detector connected to the mainoscillator and the vernier oscillator for indicating phase coincidenceof the two oscillators, a ring circuit connected to the plurality ofadditional control stages, said phase coincidence detector having anoutput line connected to said vernier oscillator, said additionalcontrol stages, and said ring circuit for stopping the vernieroscillator, deactivating said additional control stages, and advancingsaid ring circuit whenever said phase coincidence detector detectscoincidence of the main oscillator and the vernier oscillator, meansconnecting the ring circuit to the vernier oscillator for starting thevernier oscillator each time the ring circuit is advanced, delay meansconnected in series with the ring circuit for delaying the start of saidvernier oscillator, said ring circuit operating a given one of theadditional control stages each time it is advanced by the phasecoincidence detector, whereby the additional control stages are operatedin turn, means responsive to the operation of the last of said pluralityof additional control stages for stopping the main oscillator.
 9. Theapparatus of claim 8 wherein the phase coincidence detector includes: adigital integrator which responds to overlapped signals from the mainoscillator and the vernier oscillator to deactivate the phasecoincidence detector, and an analog integrator which responds tooverlapped signals from the main oscillator and the vernier oscillatorto detect phase coincidence of said main and vernier oscillators andactivate the phase coincidence detector.
 10. The apparatus of claim 9wherein the digital integrator is a single shot, and the analogintegrator is a condenser and a resistor connected in parallel.
 11. Theapparatus of claim 10 wherein the digital integrator includes aflip-flop having one and zero inputs, said single shot having an outputline connected to the one input of the flip-flop, a differentialamplifier having two inputs, means connecting the analog integrator toone of said inputs, a fixed source of bias potential connected to theother input of said differential amplifier, said differential amplifierhaving an output connected to the zero input of said flip-flop, saidflip-flop having a zero output line connected to said vernier oscillatorand said control stages for stopping said vernier oscillator anddeactivating said control stages.
 12. The apparatus of claim 11 whereinthe phase coincidence detector includes an AND circuit connected toreceive signals from the main oscillator and the vernier oscillator, andsaid AND circuit having an output line connected to said single shot andsaid analog integrator.